In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). One technique for generating multiple clock signals having a phase spacing that is smaller than a delay element is to interpolate between the delay stage phases. Phase interpolators are typically controlled by an N bit interpolation control word that selects a desired one of 2N possible phases. In one typical implementation, the phase interpolator comprises 2N dedicated interpolators, each associated with a given desired phase, and the array of 2N interpolator outputs are multiplexed to select the desired clock phase. Such an array of 2N interpolators, however, consumes considerable area and power, especially as the number of interpolated phases increases.
In another common implementation, a single interpolator is comprised of N weighted current sources that are selectively turned on or off, in accordance with the applied N bit interpolation control word, to obtain the desired clock phase. When a given current source is turned off, however, it takes time for the transistor drain to turn back on and reach steady state. With 90 nM transistor technology, for example, it has been found that the time it takes to switch from one phase to another desired phase is too slow (on the order of greater than 500 ps).
A need therefore exists for improved techniques for interpolating two input clock signals to generate a clock signal having a phase between the phase of the two input clock signals. A further need exists for improved interpolation techniques that provide fast-switching variable clock phases, and a highly linear phase interpolation transfer function, while utilizing less power and area.